Present day computer systems often contain circuitry having more than one logic family to achieve advantages associated with the families used. For example, ECL circuits, which are generally faster than CMOS circuits, have higher price and lower densities associated therewith. Good circuit design which includes both ECL and CMOS circuitry uses each logic family where its advantages are greatest when considering the design criteria.
ECL circuits have logic low levels of approximately -1.7 volts, and logic high levels of approximately -0.9 volts. In contrast, the CMOS logic low voltage level is approximately -5.2 volts and the logic high voltage level is approximately 0 volts. Therefore, when coupling an ECL circuit to a CMOS circuit, the ECL logic levels must be translated to the CMOS logic levels.
It has been observed that ECL circuitry is sensitive to ambient temperature, so that ECL logic levels are temperature dependent. Because of temperature-induced shifts in logic levels, prior art logic level translators must operate with a smaller than desirable noise margin, resulting in reduced performance.